はじめてのひき - FizzBuzzAsm_spu Diff
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! Version
% spu-gcc -v
Using built-in specs.
Target: spu
Configured with: ../toolchain/gcc/configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --disable-shared --disable-threads --disable-checking --with-headers --with-system-zlib --with-newlib --enable-languages=c,c++,fortran --disable-nls --enable-version-specific-runtime-libs --disable-libssp --program-prefix=spu- --target=spu
Thread model: single
gcc version 4.1.1
! Optimized
fizzbuzz.o: file format elf32-spu
Disassembly of section .text:
00000000 <main>:
0: 40 20 00 7f nop $127
4: 24 ff c0 d0 stqd $80,-16($1)
8: 40 80 00 d0 il $80,1
c: 24 ff 80 d1 stqd $81,-32($1)
10: 40 20 00 7f nop $127
14: 35 90 00 00 hbrp 14 <main+0x14>,$0
18: 40 80 07 d1 il $81,15
1c: 24 ff 40 d2 stqd $82,-48($1)
20: 40 80 02 d2 il $82,5
24: 24 ff 00 d3 stqd $83,-64($1)
28: 40 80 01 d3 il $83,3
2c: 24 00 40 80 stqd $0,16($1)
30: 24 fe 80 81 stqd $1,-96($1)
34: 1c e8 00 81 ai $1,$1,-96
38: 35 90 00 00 hbrp 38 <main+0x38>,$0
3c: 7f 00 28 80 heqi $0,$81,0
40: 12 00 08 9a hbrr a8 <main+0xa8>,84 <main+0x84> # 84
44: 0c 00 28 08 sfi $8,$80,0
48: 0c 00 28 89 sfi $9,$81,0
4c: 4c ff e8 0a cgti $10,$80,-1
50: 4c ff e8 8b cgti $11,$81,-1
54: 81 14 04 0a selb $8,$8,$80,$10
58: 81 34 44 8b selb $9,$9,$81,$11
5c: 54 a0 04 04 clz $4,$8
60: 54 a0 04 87 clz $7,$9
64: 40 80 00 85 il $5,1
68: 32 80 00 03 fsmbi $3,0
6c: 08 01 c2 07 sf $7,$4,$7
70: 3f e0 04 02 shlqbyi $2,$8,0
74: 48 22 c5 0b xor $11,$10,$11
78: 0b 61 c2 85 shl $5,$5,$7
7c: 0b 61 c4 84 shl $4,$9,$7
80: 00 20 00 00 lnop
84: 08 21 41 8c or $12,$3,$5
88: 3f 3f c2 85 rotqmbii $5,$5,-1
8c: 58 00 82 06 clgt $6,$4,$2
90: 00 20 00 00 lnop
94: 08 00 82 07 sf $7,$4,$2
98: 3f 3f c2 04 rotqmbii $4,$4,-1
9c: 80 60 c6 06 selb $3,$12,$3,$6
a0: 00 20 00 00 lnop
a4: 80 40 83 86 selb $2,$7,$2,$6
a8: 21 7f fb 85 brnz $5,84 <main+0x84> # 84
ac: 0c 00 01 08 sfi $8,$2,0
b0: 0c 00 01 89 sfi $9,$3,0
b4: 80 40 84 0a selb $2,$8,$2,$10
b8: 80 62 41 8b selb $3,$3,$9,$11
bc: 21 00 02 02 brnz $2,cc <main+0xcc> # cc
c0: 42 00 00 03 ila $3,0
c0: SPU_ADDR18 .rodata.str1.16
c4: 33 00 00 00 brsl $0,0
c4: SPU_REL16 puts
c8: 32 00 26 80 br 1fc <main+0x1fc> # 1fc
cc: 7f 00 29 00 heqi $0,$82,0
d0: 12 00 08 9a hbrr 138 <main+0x138>,114 <main+0x114> # 114
d4: 0c 00 28 08 sfi $8,$80,0
d8: 0c 00 29 09 sfi $9,$82,0
dc: 4c ff e8 0a cgti $10,$80,-1
e0: 4c ff e9 0b cgti $11,$82,-1
e4: 81 14 04 0a selb $8,$8,$80,$10
e8: 81 34 84 8b selb $9,$9,$82,$11
ec: 54 a0 04 04 clz $4,$8
f0: 54 a0 04 87 clz $7,$9
f4: 40 80 00 85 il $5,1
f8: 32 80 00 03 fsmbi $3,0
fc: 08 01 c2 07 sf $7,$4,$7
100: 3f e0 04 0d shlqbyi $13,$8,0
104: 48 22 c5 0b xor $11,$10,$11
108: 0b 61 c2 85 shl $5,$5,$7
10c: 0b 61 c4 84 shl $4,$9,$7
110: 00 20 00 00 lnop
114: 08 21 41 8c or $12,$3,$5
118: 3f 3f c2 85 rotqmbii $5,$5,-1
11c: 58 03 42 06 clgt $6,$4,$13
120: 00 20 00 00 lnop
124: 08 03 42 07 sf $7,$4,$13
128: 3f 3f c2 04 rotqmbii $4,$4,-1
12c: 80 60 c6 06 selb $3,$12,$3,$6
130: 00 20 00 00 lnop
134: 81 a3 43 86 selb $13,$7,$13,$6
138: 21 7f fb 85 brnz $5,114 <main+0x114> # 114
13c: 0c 00 06 88 sfi $8,$13,0
140: 0c 00 01 89 sfi $9,$3,0
144: 81 a3 44 0a selb $13,$8,$13,$10
148: 80 62 41 8b selb $3,$3,$9,$11
14c: 21 00 02 0d brnz $13,15c <main+0x15c> # 15c
150: 42 00 00 03 ila $3,0
150: SPU_ADDR18 .rodata.str1.16+0x10
154: 33 00 00 00 brsl $0,0
154: SPU_REL16 puts
158: 32 00 14 80 br 1fc <main+0x1fc> # 1fc
15c: 7f 00 29 80 heqi $0,$83,0
160: 12 00 08 9a hbrr 1c8 <main+0x1c8>,1a4 <main+0x1a4> # 1a4
164: 0c 00 28 08 sfi $8,$80,0
168: 0c 00 29 89 sfi $9,$83,0
16c: 4c ff e8 0a cgti $10,$80,-1
170: 4c ff e9 8b cgti $11,$83,-1
174: 81 14 04 0a selb $8,$8,$80,$10
178: 81 34 c4 8b selb $9,$9,$83,$11
17c: 54 a0 04 04 clz $4,$8
180: 54 a0 04 87 clz $7,$9
184: 40 80 00 85 il $5,1
188: 32 80 00 03 fsmbi $3,0
18c: 08 01 c2 07 sf $7,$4,$7
190: 3f e0 04 0e shlqbyi $14,$8,0
194: 48 22 c5 0b xor $11,$10,$11
198: 0b 61 c2 85 shl $5,$5,$7
19c: 0b 61 c4 84 shl $4,$9,$7
1a0: 00 20 00 00 lnop
1a4: 08 21 41 8c or $12,$3,$5
1a8: 3f 3f c2 85 rotqmbii $5,$5,-1
1ac: 58 03 82 06 clgt $6,$4,$14
1b0: 00 20 00 00 lnop
1b4: 08 03 82 07 sf $7,$4,$14
1b8: 3f 3f c2 04 rotqmbii $4,$4,-1
1bc: 80 60 c6 06 selb $3,$12,$3,$6
1c0: 00 20 00 00 lnop
1c4: 81 c3 83 86 selb $14,$7,$14,$6
1c8: 21 7f fb 85 brnz $5,1a4 <main+0x1a4> # 1a4
1cc: 0c 00 07 08 sfi $8,$14,0
1d0: 0c 00 01 89 sfi $9,$3,0
1d4: 81 c3 84 0a selb $14,$8,$14,$10
1d8: 80 62 41 8b selb $3,$3,$9,$11
1dc: 21 00 02 8e brnz $14,1f0 <main+0x1f0> # 1f0
1e0: 42 00 00 03 ila $3,0
1e0: SPU_ADDR18 .rodata.str1.16+0x20
1e4: 33 00 00 00 brsl $0,0
1e4: SPU_REL16 puts
1e8: 40 20 00 7f nop $127
1ec: 32 00 02 00 br 1fc <main+0x1fc> # 1fc
1f0: 42 00 00 03 ila $3,0
1f0: SPU_ADDR18 .rodata.str1.16+0x30
1f4: 3f e0 28 04 shlqbyi $4,$80,0
1f8: 33 00 00 00 brsl $0,0
1f8: SPU_REL16 printf
1fc: 1c 00 68 50 ai $80,$80,1
200: 7c 19 68 03 ceqi $3,$80,101 # 65
204: 20 7f c6 83 brz $3,38 <main+0x38> # 38
208: 1c 18 00 81 ai $1,$1,96 # 60
20c: 34 00 40 80 lqd $0,16($1)
210: 34 ff c0 d0 lqd $80,-16($1)
214: 34 ff 80 d1 lqd $81,-32($1)
218: 34 ff 40 d2 lqd $82,-48($1)
21c: 34 ff 00 d3 lqd $83,-64($1)
220: 35 00 00 00 bi $0
224: 00 20 00 00 lnop
! Normal
fizzbuzz.o: file format elf32-spu
Disassembly of section .text:
00000000 <main>:
0: 24 00 40 80 stqd $0,16($1)
4: 24 ff 40 81 stqd $1,-48($1)
8: 1c f4 00 81 ai $1,$1,-48
c: 40 80 00 82 il $2,1
10: 34 00 80 83 lqd $3,32($1) # 20
14: 3e c0 00 84 cwd $4,0($1)
18: b0 60 c1 04 shufb $3,$2,$3,$4
1c: 24 00 80 83 stqd $3,32($1) # 20
20: 32 00 41 80 br 22c <main+0x22c> # 22c
24: 34 00 80 82 lqd $2,32($1) # 20
28: 04 00 01 03 ori $3,$2,0
2c: 40 80 07 82 il $2,15
30: 7f 00 01 00 heqi $0,$2,0
34: 12 00 08 9a hbrr 9c <main+0x9c>,78 <main+0x78> # 78
38: 0c 00 01 8a sfi $10,$3,0
3c: 0c 00 01 0b sfi $11,$2,0
40: 4c ff c1 8c cgti $12,$3,-1
44: 4c ff c1 0d cgti $13,$2,-1
48: 81 40 c5 0c selb $10,$10,$3,$12
4c: 81 60 85 8d selb $11,$11,$2,$13
50: 54 a0 05 06 clz $6,$10
54: 54 a0 05 89 clz $9,$11
58: 40 80 00 87 il $7,1
5c: 32 80 00 04 fsmbi $4,0
60: 08 02 43 09 sf $9,$6,$9
64: 3f e0 05 05 shlqbyi $5,$10,0
68: 48 23 46 0d xor $13,$12,$13
6c: 0b 62 43 87 shl $7,$7,$9
70: 0b 62 45 86 shl $6,$11,$9
74: 00 20 00 00 lnop
78: 08 21 c2 0e or $14,$4,$7
7c: 3f 3f c3 87 rotqmbii $7,$7,-1
80: 58 01 43 08 clgt $8,$6,$5
84: 00 20 00 00 lnop
88: 08 01 43 09 sf $9,$6,$5
8c: 3f 3f c3 06 rotqmbii $6,$6,-1
90: 80 81 07 08 selb $4,$14,$4,$8
94: 00 20 00 00 lnop
98: 80 a1 44 88 selb $5,$9,$5,$8
9c: 21 7f fb 87 brnz $7,78 <main+0x78> # 78
a0: 0c 00 02 8a sfi $10,$5,0
a4: 0c 00 02 0b sfi $11,$4,0
a8: 80 a1 45 0c selb $5,$10,$5,$12
ac: 80 82 c2 0d selb $4,$4,$11,$13
b0: 04 00 02 82 ori $2,$5,0
b4: 21 00 02 02 brnz $2,c4 <main+0xc4> # c4
b8: 42 00 00 03 ila $3,0
b8: SPU_ADDR18 .rodata
bc: 33 00 00 00 brsl $0,0
bc: SPU_REL16 puts
c0: 32 00 2a 80 br 214 <main+0x214> # 214
c4: 34 00 80 82 lqd $2,32($1) # 20
c8: 04 00 01 03 ori $3,$2,0
cc: 40 80 02 82 il $2,5
d0: 7f 00 01 00 heqi $0,$2,0
d4: 12 00 08 9a hbrr 13c <main+0x13c>,118 <main+0x118> # 118
d8: 0c 00 01 8a sfi $10,$3,0
dc: 0c 00 01 0b sfi $11,$2,0
e0: 4c ff c1 8c cgti $12,$3,-1
e4: 4c ff c1 0d cgti $13,$2,-1
e8: 81 40 c5 0c selb $10,$10,$3,$12
ec: 81 60 85 8d selb $11,$11,$2,$13
f0: 54 a0 05 06 clz $6,$10
f4: 54 a0 05 89 clz $9,$11
f8: 40 80 00 87 il $7,1
fc: 32 80 00 04 fsmbi $4,0
100: 08 02 43 09 sf $9,$6,$9
104: 3f e0 05 05 shlqbyi $5,$10,0
108: 48 23 46 0d xor $13,$12,$13
10c: 0b 62 43 87 shl $7,$7,$9
110: 0b 62 45 86 shl $6,$11,$9
114: 00 20 00 00 lnop
118: 08 21 c2 0e or $14,$4,$7
11c: 3f 3f c3 87 rotqmbii $7,$7,-1
120: 58 01 43 08 clgt $8,$6,$5
124: 00 20 00 00 lnop
128: 08 01 43 09 sf $9,$6,$5
12c: 3f 3f c3 06 rotqmbii $6,$6,-1
130: 80 81 07 08 selb $4,$14,$4,$8
134: 00 20 00 00 lnop
138: 80 a1 44 88 selb $5,$9,$5,$8
13c: 21 7f fb 87 brnz $7,118 <main+0x118> # 118
140: 0c 00 02 8a sfi $10,$5,0
144: 0c 00 02 0b sfi $11,$4,0
148: 80 a1 45 0c selb $5,$10,$5,$12
14c: 80 82 c2 0d selb $4,$4,$11,$13
150: 04 00 02 82 ori $2,$5,0
154: 21 00 02 02 brnz $2,164 <main+0x164> # 164
158: 42 00 00 03 ila $3,0
158: SPU_ADDR18 .rodata+0x10
15c: 33 00 00 00 brsl $0,0
15c: SPU_REL16 puts
160: 32 00 16 80 br 214 <main+0x214> # 214
164: 34 00 80 82 lqd $2,32($1) # 20
168: 04 00 01 03 ori $3,$2,0
16c: 40 80 01 82 il $2,3
170: 7f 00 01 00 heqi $0,$2,0
174: 12 00 08 9a hbrr 1dc <main+0x1dc>,1b8 <main+0x1b8> # 1b8
178: 0c 00 01 8a sfi $10,$3,0
17c: 0c 00 01 0b sfi $11,$2,0
180: 4c ff c1 8c cgti $12,$3,-1
184: 4c ff c1 0d cgti $13,$2,-1
188: 81 40 c5 0c selb $10,$10,$3,$12
18c: 81 60 85 8d selb $11,$11,$2,$13
190: 54 a0 05 06 clz $6,$10
194: 54 a0 05 89 clz $9,$11
198: 40 80 00 87 il $7,1
19c: 32 80 00 04 fsmbi $4,0
1a0: 08 02 43 09 sf $9,$6,$9
1a4: 3f e0 05 05 shlqbyi $5,$10,0
1a8: 48 23 46 0d xor $13,$12,$13
1ac: 0b 62 43 87 shl $7,$7,$9
1b0: 0b 62 45 86 shl $6,$11,$9
1b4: 00 20 00 00 lnop
1b8: 08 21 c2 0e or $14,$4,$7
1bc: 3f 3f c3 87 rotqmbii $7,$7,-1
1c0: 58 01 43 08 clgt $8,$6,$5
1c4: 00 20 00 00 lnop
1c8: 08 01 43 09 sf $9,$6,$5
1cc: 3f 3f c3 06 rotqmbii $6,$6,-1
1d0: 80 81 07 08 selb $4,$14,$4,$8
1d4: 00 20 00 00 lnop
1d8: 80 a1 44 88 selb $5,$9,$5,$8
1dc: 21 7f fb 87 brnz $7,1b8 <main+0x1b8> # 1b8
1e0: 0c 00 02 8a sfi $10,$5,0
1e4: 0c 00 02 0b sfi $11,$4,0
1e8: 80 a1 45 0c selb $5,$10,$5,$12
1ec: 80 82 c2 0d selb $4,$4,$11,$13
1f0: 04 00 02 82 ori $2,$5,0
1f4: 21 00 02 02 brnz $2,204 <main+0x204> # 204
1f8: 42 00 00 03 ila $3,0
1f8: SPU_ADDR18 .rodata+0x20
1fc: 33 00 00 00 brsl $0,0
1fc: SPU_REL16 puts
200: 32 00 02 80 br 214 <main+0x214> # 214
204: 42 00 00 03 ila $3,0
204: SPU_ADDR18 .rodata+0x30
208: 34 00 80 82 lqd $2,32($1) # 20
20c: 04 00 01 04 ori $4,$2,0
210: 33 00 00 00 brsl $0,0
210: SPU_REL16 printf
214: 34 00 80 82 lqd $2,32($1) # 20
218: 1c 00 41 04 ai $4,$2,1
21c: 34 00 80 82 lqd $2,32($1) # 20
220: 3e c0 00 83 cwd $3,0($1)
224: b0 40 82 03 shufb $2,$4,$2,$3
228: 24 00 80 82 stqd $2,32($1) # 20
22c: 34 00 80 82 lqd $2,32($1) # 20
230: 4c 19 01 02 cgti $2,$2,100 # 64
234: 20 7f be 02 brz $2,24 <main+0x24> # 24
238: 1c 0c 00 81 ai $1,$1,48 # 30
23c: 34 00 40 80 lqd $0,16($1)
240: 35 00 00 00 bi $0
244: 00 20 00 00 lnop
% spu-gcc -v
Using built-in specs.
Target: spu
Configured with: ../toolchain/gcc/configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --disable-shared --disable-threads --disable-checking --with-headers --with-system-zlib --with-newlib --enable-languages=c,c++,fortran --disable-nls --enable-version-specific-runtime-libs --disable-libssp --program-prefix=spu- --target=spu
Thread model: single
gcc version 4.1.1
! Optimized
fizzbuzz.o: file format elf32-spu
Disassembly of section .text:
00000000 <main>:
0: 40 20 00 7f nop $127
4: 24 ff c0 d0 stqd $80,-16($1)
8: 40 80 00 d0 il $80,1
c: 24 ff 80 d1 stqd $81,-32($1)
10: 40 20 00 7f nop $127
14: 35 90 00 00 hbrp 14 <main+0x14>,$0
18: 40 80 07 d1 il $81,15
1c: 24 ff 40 d2 stqd $82,-48($1)
20: 40 80 02 d2 il $82,5
24: 24 ff 00 d3 stqd $83,-64($1)
28: 40 80 01 d3 il $83,3
2c: 24 00 40 80 stqd $0,16($1)
30: 24 fe 80 81 stqd $1,-96($1)
34: 1c e8 00 81 ai $1,$1,-96
38: 35 90 00 00 hbrp 38 <main+0x38>,$0
3c: 7f 00 28 80 heqi $0,$81,0
40: 12 00 08 9a hbrr a8 <main+0xa8>,84 <main+0x84> # 84
44: 0c 00 28 08 sfi $8,$80,0
48: 0c 00 28 89 sfi $9,$81,0
4c: 4c ff e8 0a cgti $10,$80,-1
50: 4c ff e8 8b cgti $11,$81,-1
54: 81 14 04 0a selb $8,$8,$80,$10
58: 81 34 44 8b selb $9,$9,$81,$11
5c: 54 a0 04 04 clz $4,$8
60: 54 a0 04 87 clz $7,$9
64: 40 80 00 85 il $5,1
68: 32 80 00 03 fsmbi $3,0
6c: 08 01 c2 07 sf $7,$4,$7
70: 3f e0 04 02 shlqbyi $2,$8,0
74: 48 22 c5 0b xor $11,$10,$11
78: 0b 61 c2 85 shl $5,$5,$7
7c: 0b 61 c4 84 shl $4,$9,$7
80: 00 20 00 00 lnop
84: 08 21 41 8c or $12,$3,$5
88: 3f 3f c2 85 rotqmbii $5,$5,-1
8c: 58 00 82 06 clgt $6,$4,$2
90: 00 20 00 00 lnop
94: 08 00 82 07 sf $7,$4,$2
98: 3f 3f c2 04 rotqmbii $4,$4,-1
9c: 80 60 c6 06 selb $3,$12,$3,$6
a0: 00 20 00 00 lnop
a4: 80 40 83 86 selb $2,$7,$2,$6
a8: 21 7f fb 85 brnz $5,84 <main+0x84> # 84
ac: 0c 00 01 08 sfi $8,$2,0
b0: 0c 00 01 89 sfi $9,$3,0
b4: 80 40 84 0a selb $2,$8,$2,$10
b8: 80 62 41 8b selb $3,$3,$9,$11
bc: 21 00 02 02 brnz $2,cc <main+0xcc> # cc
c0: 42 00 00 03 ila $3,0
c0: SPU_ADDR18 .rodata.str1.16
c4: 33 00 00 00 brsl $0,0
c4: SPU_REL16 puts
c8: 32 00 26 80 br 1fc <main+0x1fc> # 1fc
cc: 7f 00 29 00 heqi $0,$82,0
d0: 12 00 08 9a hbrr 138 <main+0x138>,114 <main+0x114> # 114
d4: 0c 00 28 08 sfi $8,$80,0
d8: 0c 00 29 09 sfi $9,$82,0
dc: 4c ff e8 0a cgti $10,$80,-1
e0: 4c ff e9 0b cgti $11,$82,-1
e4: 81 14 04 0a selb $8,$8,$80,$10
e8: 81 34 84 8b selb $9,$9,$82,$11
ec: 54 a0 04 04 clz $4,$8
f0: 54 a0 04 87 clz $7,$9
f4: 40 80 00 85 il $5,1
f8: 32 80 00 03 fsmbi $3,0
fc: 08 01 c2 07 sf $7,$4,$7
100: 3f e0 04 0d shlqbyi $13,$8,0
104: 48 22 c5 0b xor $11,$10,$11
108: 0b 61 c2 85 shl $5,$5,$7
10c: 0b 61 c4 84 shl $4,$9,$7
110: 00 20 00 00 lnop
114: 08 21 41 8c or $12,$3,$5
118: 3f 3f c2 85 rotqmbii $5,$5,-1
11c: 58 03 42 06 clgt $6,$4,$13
120: 00 20 00 00 lnop
124: 08 03 42 07 sf $7,$4,$13
128: 3f 3f c2 04 rotqmbii $4,$4,-1
12c: 80 60 c6 06 selb $3,$12,$3,$6
130: 00 20 00 00 lnop
134: 81 a3 43 86 selb $13,$7,$13,$6
138: 21 7f fb 85 brnz $5,114 <main+0x114> # 114
13c: 0c 00 06 88 sfi $8,$13,0
140: 0c 00 01 89 sfi $9,$3,0
144: 81 a3 44 0a selb $13,$8,$13,$10
148: 80 62 41 8b selb $3,$3,$9,$11
14c: 21 00 02 0d brnz $13,15c <main+0x15c> # 15c
150: 42 00 00 03 ila $3,0
150: SPU_ADDR18 .rodata.str1.16+0x10
154: 33 00 00 00 brsl $0,0
154: SPU_REL16 puts
158: 32 00 14 80 br 1fc <main+0x1fc> # 1fc
15c: 7f 00 29 80 heqi $0,$83,0
160: 12 00 08 9a hbrr 1c8 <main+0x1c8>,1a4 <main+0x1a4> # 1a4
164: 0c 00 28 08 sfi $8,$80,0
168: 0c 00 29 89 sfi $9,$83,0
16c: 4c ff e8 0a cgti $10,$80,-1
170: 4c ff e9 8b cgti $11,$83,-1
174: 81 14 04 0a selb $8,$8,$80,$10
178: 81 34 c4 8b selb $9,$9,$83,$11
17c: 54 a0 04 04 clz $4,$8
180: 54 a0 04 87 clz $7,$9
184: 40 80 00 85 il $5,1
188: 32 80 00 03 fsmbi $3,0
18c: 08 01 c2 07 sf $7,$4,$7
190: 3f e0 04 0e shlqbyi $14,$8,0
194: 48 22 c5 0b xor $11,$10,$11
198: 0b 61 c2 85 shl $5,$5,$7
19c: 0b 61 c4 84 shl $4,$9,$7
1a0: 00 20 00 00 lnop
1a4: 08 21 41 8c or $12,$3,$5
1a8: 3f 3f c2 85 rotqmbii $5,$5,-1
1ac: 58 03 82 06 clgt $6,$4,$14
1b0: 00 20 00 00 lnop
1b4: 08 03 82 07 sf $7,$4,$14
1b8: 3f 3f c2 04 rotqmbii $4,$4,-1
1bc: 80 60 c6 06 selb $3,$12,$3,$6
1c0: 00 20 00 00 lnop
1c4: 81 c3 83 86 selb $14,$7,$14,$6
1c8: 21 7f fb 85 brnz $5,1a4 <main+0x1a4> # 1a4
1cc: 0c 00 07 08 sfi $8,$14,0
1d0: 0c 00 01 89 sfi $9,$3,0
1d4: 81 c3 84 0a selb $14,$8,$14,$10
1d8: 80 62 41 8b selb $3,$3,$9,$11
1dc: 21 00 02 8e brnz $14,1f0 <main+0x1f0> # 1f0
1e0: 42 00 00 03 ila $3,0
1e0: SPU_ADDR18 .rodata.str1.16+0x20
1e4: 33 00 00 00 brsl $0,0
1e4: SPU_REL16 puts
1e8: 40 20 00 7f nop $127
1ec: 32 00 02 00 br 1fc <main+0x1fc> # 1fc
1f0: 42 00 00 03 ila $3,0
1f0: SPU_ADDR18 .rodata.str1.16+0x30
1f4: 3f e0 28 04 shlqbyi $4,$80,0
1f8: 33 00 00 00 brsl $0,0
1f8: SPU_REL16 printf
1fc: 1c 00 68 50 ai $80,$80,1
200: 7c 19 68 03 ceqi $3,$80,101 # 65
204: 20 7f c6 83 brz $3,38 <main+0x38> # 38
208: 1c 18 00 81 ai $1,$1,96 # 60
20c: 34 00 40 80 lqd $0,16($1)
210: 34 ff c0 d0 lqd $80,-16($1)
214: 34 ff 80 d1 lqd $81,-32($1)
218: 34 ff 40 d2 lqd $82,-48($1)
21c: 34 ff 00 d3 lqd $83,-64($1)
220: 35 00 00 00 bi $0
224: 00 20 00 00 lnop
! Normal
fizzbuzz.o: file format elf32-spu
Disassembly of section .text:
00000000 <main>:
0: 24 00 40 80 stqd $0,16($1)
4: 24 ff 40 81 stqd $1,-48($1)
8: 1c f4 00 81 ai $1,$1,-48
c: 40 80 00 82 il $2,1
10: 34 00 80 83 lqd $3,32($1) # 20
14: 3e c0 00 84 cwd $4,0($1)
18: b0 60 c1 04 shufb $3,$2,$3,$4
1c: 24 00 80 83 stqd $3,32($1) # 20
20: 32 00 41 80 br 22c <main+0x22c> # 22c
24: 34 00 80 82 lqd $2,32($1) # 20
28: 04 00 01 03 ori $3,$2,0
2c: 40 80 07 82 il $2,15
30: 7f 00 01 00 heqi $0,$2,0
34: 12 00 08 9a hbrr 9c <main+0x9c>,78 <main+0x78> # 78
38: 0c 00 01 8a sfi $10,$3,0
3c: 0c 00 01 0b sfi $11,$2,0
40: 4c ff c1 8c cgti $12,$3,-1
44: 4c ff c1 0d cgti $13,$2,-1
48: 81 40 c5 0c selb $10,$10,$3,$12
4c: 81 60 85 8d selb $11,$11,$2,$13
50: 54 a0 05 06 clz $6,$10
54: 54 a0 05 89 clz $9,$11
58: 40 80 00 87 il $7,1
5c: 32 80 00 04 fsmbi $4,0
60: 08 02 43 09 sf $9,$6,$9
64: 3f e0 05 05 shlqbyi $5,$10,0
68: 48 23 46 0d xor $13,$12,$13
6c: 0b 62 43 87 shl $7,$7,$9
70: 0b 62 45 86 shl $6,$11,$9
74: 00 20 00 00 lnop
78: 08 21 c2 0e or $14,$4,$7
7c: 3f 3f c3 87 rotqmbii $7,$7,-1
80: 58 01 43 08 clgt $8,$6,$5
84: 00 20 00 00 lnop
88: 08 01 43 09 sf $9,$6,$5
8c: 3f 3f c3 06 rotqmbii $6,$6,-1
90: 80 81 07 08 selb $4,$14,$4,$8
94: 00 20 00 00 lnop
98: 80 a1 44 88 selb $5,$9,$5,$8
9c: 21 7f fb 87 brnz $7,78 <main+0x78> # 78
a0: 0c 00 02 8a sfi $10,$5,0
a4: 0c 00 02 0b sfi $11,$4,0
a8: 80 a1 45 0c selb $5,$10,$5,$12
ac: 80 82 c2 0d selb $4,$4,$11,$13
b0: 04 00 02 82 ori $2,$5,0
b4: 21 00 02 02 brnz $2,c4 <main+0xc4> # c4
b8: 42 00 00 03 ila $3,0
b8: SPU_ADDR18 .rodata
bc: 33 00 00 00 brsl $0,0
bc: SPU_REL16 puts
c0: 32 00 2a 80 br 214 <main+0x214> # 214
c4: 34 00 80 82 lqd $2,32($1) # 20
c8: 04 00 01 03 ori $3,$2,0
cc: 40 80 02 82 il $2,5
d0: 7f 00 01 00 heqi $0,$2,0
d4: 12 00 08 9a hbrr 13c <main+0x13c>,118 <main+0x118> # 118
d8: 0c 00 01 8a sfi $10,$3,0
dc: 0c 00 01 0b sfi $11,$2,0
e0: 4c ff c1 8c cgti $12,$3,-1
e4: 4c ff c1 0d cgti $13,$2,-1
e8: 81 40 c5 0c selb $10,$10,$3,$12
ec: 81 60 85 8d selb $11,$11,$2,$13
f0: 54 a0 05 06 clz $6,$10
f4: 54 a0 05 89 clz $9,$11
f8: 40 80 00 87 il $7,1
fc: 32 80 00 04 fsmbi $4,0
100: 08 02 43 09 sf $9,$6,$9
104: 3f e0 05 05 shlqbyi $5,$10,0
108: 48 23 46 0d xor $13,$12,$13
10c: 0b 62 43 87 shl $7,$7,$9
110: 0b 62 45 86 shl $6,$11,$9
114: 00 20 00 00 lnop
118: 08 21 c2 0e or $14,$4,$7
11c: 3f 3f c3 87 rotqmbii $7,$7,-1
120: 58 01 43 08 clgt $8,$6,$5
124: 00 20 00 00 lnop
128: 08 01 43 09 sf $9,$6,$5
12c: 3f 3f c3 06 rotqmbii $6,$6,-1
130: 80 81 07 08 selb $4,$14,$4,$8
134: 00 20 00 00 lnop
138: 80 a1 44 88 selb $5,$9,$5,$8
13c: 21 7f fb 87 brnz $7,118 <main+0x118> # 118
140: 0c 00 02 8a sfi $10,$5,0
144: 0c 00 02 0b sfi $11,$4,0
148: 80 a1 45 0c selb $5,$10,$5,$12
14c: 80 82 c2 0d selb $4,$4,$11,$13
150: 04 00 02 82 ori $2,$5,0
154: 21 00 02 02 brnz $2,164 <main+0x164> # 164
158: 42 00 00 03 ila $3,0
158: SPU_ADDR18 .rodata+0x10
15c: 33 00 00 00 brsl $0,0
15c: SPU_REL16 puts
160: 32 00 16 80 br 214 <main+0x214> # 214
164: 34 00 80 82 lqd $2,32($1) # 20
168: 04 00 01 03 ori $3,$2,0
16c: 40 80 01 82 il $2,3
170: 7f 00 01 00 heqi $0,$2,0
174: 12 00 08 9a hbrr 1dc <main+0x1dc>,1b8 <main+0x1b8> # 1b8
178: 0c 00 01 8a sfi $10,$3,0
17c: 0c 00 01 0b sfi $11,$2,0
180: 4c ff c1 8c cgti $12,$3,-1
184: 4c ff c1 0d cgti $13,$2,-1
188: 81 40 c5 0c selb $10,$10,$3,$12
18c: 81 60 85 8d selb $11,$11,$2,$13
190: 54 a0 05 06 clz $6,$10
194: 54 a0 05 89 clz $9,$11
198: 40 80 00 87 il $7,1
19c: 32 80 00 04 fsmbi $4,0
1a0: 08 02 43 09 sf $9,$6,$9
1a4: 3f e0 05 05 shlqbyi $5,$10,0
1a8: 48 23 46 0d xor $13,$12,$13
1ac: 0b 62 43 87 shl $7,$7,$9
1b0: 0b 62 45 86 shl $6,$11,$9
1b4: 00 20 00 00 lnop
1b8: 08 21 c2 0e or $14,$4,$7
1bc: 3f 3f c3 87 rotqmbii $7,$7,-1
1c0: 58 01 43 08 clgt $8,$6,$5
1c4: 00 20 00 00 lnop
1c8: 08 01 43 09 sf $9,$6,$5
1cc: 3f 3f c3 06 rotqmbii $6,$6,-1
1d0: 80 81 07 08 selb $4,$14,$4,$8
1d4: 00 20 00 00 lnop
1d8: 80 a1 44 88 selb $5,$9,$5,$8
1dc: 21 7f fb 87 brnz $7,1b8 <main+0x1b8> # 1b8
1e0: 0c 00 02 8a sfi $10,$5,0
1e4: 0c 00 02 0b sfi $11,$4,0
1e8: 80 a1 45 0c selb $5,$10,$5,$12
1ec: 80 82 c2 0d selb $4,$4,$11,$13
1f0: 04 00 02 82 ori $2,$5,0
1f4: 21 00 02 02 brnz $2,204 <main+0x204> # 204
1f8: 42 00 00 03 ila $3,0
1f8: SPU_ADDR18 .rodata+0x20
1fc: 33 00 00 00 brsl $0,0
1fc: SPU_REL16 puts
200: 32 00 02 80 br 214 <main+0x214> # 214
204: 42 00 00 03 ila $3,0
204: SPU_ADDR18 .rodata+0x30
208: 34 00 80 82 lqd $2,32($1) # 20
20c: 04 00 01 04 ori $4,$2,0
210: 33 00 00 00 brsl $0,0
210: SPU_REL16 printf
214: 34 00 80 82 lqd $2,32($1) # 20
218: 1c 00 41 04 ai $4,$2,1
21c: 34 00 80 82 lqd $2,32($1) # 20
220: 3e c0 00 83 cwd $3,0($1)
224: b0 40 82 03 shufb $2,$4,$2,$3
228: 24 00 80 82 stqd $2,32($1) # 20
22c: 34 00 80 82 lqd $2,32($1) # 20
230: 4c 19 01 02 cgti $2,$2,100 # 64
234: 20 7f be 02 brz $2,24 <main+0x24> # 24
238: 1c 0c 00 81 ai $1,$1,48 # 30
23c: 34 00 40 80 lqd $0,16($1)
240: 35 00 00 00 bi $0
244: 00 20 00 00 lnop