はじめてのひき - FizzBuzzAsm_sparc64 Diff
- Added parts are displayed like this.
- Deleted parts are displayed
like this.
! Version
% sparc64-elf-gcc -v
Using built-in specs.
Target: sparc64-elf
Configured with: ../configure elf
Thread model: single
gcc version 4.3.1 (GCC)
! Optimized
fizzbuzz.o: file format elf64-sparc
Disassembly of section .text:
0000000000000000 <main>:
0: 9d e3 bf 40 save %sp, -192, %sp
4: b0 10 20 01 mov 1, %i0
8: 03 00 00 00 sethi %hi(0), %g1
8: R_SPARC_HI22 .rodata.str1.8+0x20
c: 82 00 40 04 add %g1, %g4, %g1
10: a6 00 60 00 add %g1, 0, %l3
10: R_SPARC_LO10 .rodata.str1.8+0x20
14: 03 00 00 00 sethi %hi(0), %g1
14: R_SPARC_HI22 .rodata.str1.8+0x18
18: 82 00 40 04 add %g1, %g4, %g1
1c: a2 00 60 00 add %g1, 0, %l1
1c: R_SPARC_LO10 .rodata.str1.8+0x18
20: 03 00 00 00 sethi %hi(0), %g1
20: R_SPARC_HI22 .rodata.str1.8+0x10
24: 82 00 40 04 add %g1, %g4, %g1
28: a4 00 60 00 add %g1, 0, %l2
28: R_SPARC_LO10 .rodata.str1.8+0x10
2c: 03 00 00 00 sethi %hi(0), %g1
2c: R_SPARC_HI22 .rodata.str1.8
30: 82 00 40 04 add %g1, %g4, %g1
34: a0 00 60 00 add %g1, 0, %l0
34: R_SPARC_LO10 .rodata.str1.8
38: 87 3e 20 00 sra %i0, 0, %g3
3c: 85 68 e0 0f sdivx %g3, 0xf, %g2
40: 83 28 b0 04 sllx %g2, 4, %g1
44: 82 20 40 02 sub %g1, %g2, %g1
48: 80 a0 c0 01 cmp %g3, %g1
4c: 12 48 00 06 bne %icc, 64 <main+0x64>
50: 85 68 e0 05 sdivx %g3, 5, %g2
54: 40 00 00 00 call 54 <main+0x54>
54: R_SPARC_WDISP30 puts
58: 90 10 00 10 mov %l0, %o0
5c: 10 68 00 18 b %xcc, bc <main+0xbc>
60: b0 06 20 01 inc %i0
64: 83 28 b0 02 sllx %g2, 2, %g1
68: 82 00 40 02 add %g1, %g2, %g1
6c: 80 a0 c0 01 cmp %g3, %g1
70: 12 48 00 06 bne %icc, 88 <main+0x88>
74: 83 3e 20 00 sra %i0, 0, %g1
78: 40 00 00 00 call 78 <main+0x78>
78: R_SPARC_WDISP30 puts
7c: 90 10 00 12 mov %l2, %o0
80: 10 68 00 0f b %xcc, bc <main+0xbc>
84: b0 06 20 01 inc %i0
88: 85 68 60 03 sdivx %g1, 3, %g2
8c: 86 00 80 02 add %g2, %g2, %g3
90: 86 00 c0 02 add %g3, %g2, %g3
94: 80 a0 40 03 cmp %g1, %g3
98: 32 48 00 06 bne,a %icc, b0 <main+0xb0>
9c: 90 10 00 13 mov %l3, %o0
a0: 40 00 00 00 call a0 <main+0xa0>
a0: R_SPARC_WDISP30 puts
a4: 90 10 00 11 mov %l1, %o0
a8: 10 68 00 05 b %xcc, bc <main+0xbc>
ac: b0 06 20 01 inc %i0
b0: 40 00 00 00 call b0 <main+0xb0>
b0: R_SPARC_WDISP30 printf
b4: 93 3e 20 00 sra %i0, 0, %o1
b8: b0 06 20 01 inc %i0
bc: 80 a6 20 65 cmp %i0, 0x65
c0: 12 4f ff df bne %icc, 3c <main+0x3c>
c4: 87 3e 20 00 sra %i0, 0, %g3
c8: 81 cf e0 08 rett %i7 + 8
cc: 01 00 00 00 nop
! Normal
fizzbuzz.o: file format elf64-sparc
Disassembly of section .text:
0000000000000000 <main>:
0: 9d e3 bf 20 save %sp, -224, %sp
4: 82 10 20 01 mov 1, %g1
8: c2 27 a7 eb st %g1, [ %fp + 0x7eb ]
c: 10 68 00 40 b %xcc, 10c <main+0x10c>
10: 01 00 00 00 nop
14: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
18: 87 38 60 00 sra %g1, 0, %g3
1c: 85 68 e0 0f sdivx %g3, 0xf, %g2
20: 82 10 00 02 mov %g2, %g1
24: 83 28 70 04 sllx %g1, 4, %g1
28: 82 20 40 02 sub %g1, %g2, %g1
2c: 82 20 c0 01 sub %g3, %g1, %g1
30: 80 a0 60 00 cmp %g1, 0
34: 12 48 00 09 bne %icc, 58 <main+0x58>
38: 01 00 00 00 nop
3c: 03 00 00 00 sethi %hi(0), %g1
3c: R_SPARC_HI22 .rodata
40: 82 00 40 04 add %g1, %g4, %g1
44: 90 00 60 00 add %g1, 0, %o0
44: R_SPARC_LO10 .rodata
48: 40 00 00 00 call 48 <main+0x48>
48: R_SPARC_WDISP30 puts
4c: 01 00 00 00 nop
50: 10 68 00 2c b %xcc, 100 <main+0x100>
54: 01 00 00 00 nop
58: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
5c: 87 38 60 00 sra %g1, 0, %g3
60: 85 68 e0 05 sdivx %g3, 5, %g2
64: 82 10 00 02 mov %g2, %g1
68: 83 28 70 02 sllx %g1, 2, %g1
6c: 82 00 40 02 add %g1, %g2, %g1
70: 82 20 c0 01 sub %g3, %g1, %g1
74: 80 a0 60 00 cmp %g1, 0
78: 12 48 00 09 bne %icc, 9c <main+0x9c>
7c: 01 00 00 00 nop
80: 03 00 00 00 sethi %hi(0), %g1
80: R_SPARC_HI22 .rodata+0x10
84: 82 00 40 04 add %g1, %g4, %g1
88: 90 00 60 00 add %g1, 0, %o0
88: R_SPARC_LO10 .rodata+0x10
8c: 40 00 00 00 call 8c <main+0x8c>
8c: R_SPARC_WDISP30 puts
90: 01 00 00 00 nop
94: 10 68 00 1b b %xcc, 100 <main+0x100>
98: 01 00 00 00 nop
9c: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
a0: 87 38 60 00 sra %g1, 0, %g3
a4: 85 68 e0 03 sdivx %g3, 3, %g2
a8: 82 10 00 02 mov %g2, %g1
ac: 82 00 40 01 add %g1, %g1, %g1
b0: 82 00 40 02 add %g1, %g2, %g1
b4: 82 20 c0 01 sub %g3, %g1, %g1
b8: 80 a0 60 00 cmp %g1, 0
bc: 12 48 00 09 bne %icc, e0 <main+0xe0>
c0: 01 00 00 00 nop
c4: 03 00 00 00 sethi %hi(0), %g1
c4: R_SPARC_HI22 .rodata+0x18
c8: 82 00 40 04 add %g1, %g4, %g1
cc: 90 00 60 00 add %g1, 0, %o0
cc: R_SPARC_LO10 .rodata+0x18
d0: 40 00 00 00 call d0 <main+0xd0>
d0: R_SPARC_WDISP30 puts
d4: 01 00 00 00 nop
d8: 10 68 00 0a b %xcc, 100 <main+0x100>
dc: 01 00 00 00 nop
e0: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
e4: 85 38 60 00 sra %g1, 0, %g2
e8: 03 00 00 00 sethi %hi(0), %g1
e8: R_SPARC_HI22 .rodata+0x20
ec: 82 00 40 04 add %g1, %g4, %g1
f0: 90 00 60 00 add %g1, 0, %o0
f0: R_SPARC_LO10 .rodata+0x20
f4: 92 10 00 02 mov %g2, %o1
f8: 40 00 00 00 call f8 <main+0xf8>
f8: R_SPARC_WDISP30 printf
fc: 01 00 00 00 nop
100: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
104: 82 00 60 01 inc %g1
108: c2 27 a7 eb st %g1, [ %fp + 0x7eb ]
10c: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
110: 80 a0 60 64 cmp %g1, 0x64
114: 04 4f ff c0 ble %icc, 14 <main+0x14>
118: 01 00 00 00 nop
11c: 81 cf e0 08 rett %i7 + 8
120: 01 00 00 00 nop
% sparc64-elf-gcc -v
Using built-in specs.
Target: sparc64-elf
Configured with: ../configure elf
Thread model: single
gcc version 4.3.1 (GCC)
! Optimized
fizzbuzz.o: file format elf64-sparc
Disassembly of section .text:
0000000000000000 <main>:
0: 9d e3 bf 40 save %sp, -192, %sp
4: b0 10 20 01 mov 1, %i0
8: 03 00 00 00 sethi %hi(0), %g1
8: R_SPARC_HI22 .rodata.str1.8+0x20
c: 82 00 40 04 add %g1, %g4, %g1
10: a6 00 60 00 add %g1, 0, %l3
10: R_SPARC_LO10 .rodata.str1.8+0x20
14: 03 00 00 00 sethi %hi(0), %g1
14: R_SPARC_HI22 .rodata.str1.8+0x18
18: 82 00 40 04 add %g1, %g4, %g1
1c: a2 00 60 00 add %g1, 0, %l1
1c: R_SPARC_LO10 .rodata.str1.8+0x18
20: 03 00 00 00 sethi %hi(0), %g1
20: R_SPARC_HI22 .rodata.str1.8+0x10
24: 82 00 40 04 add %g1, %g4, %g1
28: a4 00 60 00 add %g1, 0, %l2
28: R_SPARC_LO10 .rodata.str1.8+0x10
2c: 03 00 00 00 sethi %hi(0), %g1
2c: R_SPARC_HI22 .rodata.str1.8
30: 82 00 40 04 add %g1, %g4, %g1
34: a0 00 60 00 add %g1, 0, %l0
34: R_SPARC_LO10 .rodata.str1.8
38: 87 3e 20 00 sra %i0, 0, %g3
3c: 85 68 e0 0f sdivx %g3, 0xf, %g2
40: 83 28 b0 04 sllx %g2, 4, %g1
44: 82 20 40 02 sub %g1, %g2, %g1
48: 80 a0 c0 01 cmp %g3, %g1
4c: 12 48 00 06 bne %icc, 64 <main+0x64>
50: 85 68 e0 05 sdivx %g3, 5, %g2
54: 40 00 00 00 call 54 <main+0x54>
54: R_SPARC_WDISP30 puts
58: 90 10 00 10 mov %l0, %o0
5c: 10 68 00 18 b %xcc, bc <main+0xbc>
60: b0 06 20 01 inc %i0
64: 83 28 b0 02 sllx %g2, 2, %g1
68: 82 00 40 02 add %g1, %g2, %g1
6c: 80 a0 c0 01 cmp %g3, %g1
70: 12 48 00 06 bne %icc, 88 <main+0x88>
74: 83 3e 20 00 sra %i0, 0, %g1
78: 40 00 00 00 call 78 <main+0x78>
78: R_SPARC_WDISP30 puts
7c: 90 10 00 12 mov %l2, %o0
80: 10 68 00 0f b %xcc, bc <main+0xbc>
84: b0 06 20 01 inc %i0
88: 85 68 60 03 sdivx %g1, 3, %g2
8c: 86 00 80 02 add %g2, %g2, %g3
90: 86 00 c0 02 add %g3, %g2, %g3
94: 80 a0 40 03 cmp %g1, %g3
98: 32 48 00 06 bne,a %icc, b0 <main+0xb0>
9c: 90 10 00 13 mov %l3, %o0
a0: 40 00 00 00 call a0 <main+0xa0>
a0: R_SPARC_WDISP30 puts
a4: 90 10 00 11 mov %l1, %o0
a8: 10 68 00 05 b %xcc, bc <main+0xbc>
ac: b0 06 20 01 inc %i0
b0: 40 00 00 00 call b0 <main+0xb0>
b0: R_SPARC_WDISP30 printf
b4: 93 3e 20 00 sra %i0, 0, %o1
b8: b0 06 20 01 inc %i0
bc: 80 a6 20 65 cmp %i0, 0x65
c0: 12 4f ff df bne %icc, 3c <main+0x3c>
c4: 87 3e 20 00 sra %i0, 0, %g3
c8: 81 cf e0 08 rett %i7 + 8
cc: 01 00 00 00 nop
! Normal
fizzbuzz.o: file format elf64-sparc
Disassembly of section .text:
0000000000000000 <main>:
0: 9d e3 bf 20 save %sp, -224, %sp
4: 82 10 20 01 mov 1, %g1
8: c2 27 a7 eb st %g1, [ %fp + 0x7eb ]
c: 10 68 00 40 b %xcc, 10c <main+0x10c>
10: 01 00 00 00 nop
14: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
18: 87 38 60 00 sra %g1, 0, %g3
1c: 85 68 e0 0f sdivx %g3, 0xf, %g2
20: 82 10 00 02 mov %g2, %g1
24: 83 28 70 04 sllx %g1, 4, %g1
28: 82 20 40 02 sub %g1, %g2, %g1
2c: 82 20 c0 01 sub %g3, %g1, %g1
30: 80 a0 60 00 cmp %g1, 0
34: 12 48 00 09 bne %icc, 58 <main+0x58>
38: 01 00 00 00 nop
3c: 03 00 00 00 sethi %hi(0), %g1
3c: R_SPARC_HI22 .rodata
40: 82 00 40 04 add %g1, %g4, %g1
44: 90 00 60 00 add %g1, 0, %o0
44: R_SPARC_LO10 .rodata
48: 40 00 00 00 call 48 <main+0x48>
48: R_SPARC_WDISP30 puts
4c: 01 00 00 00 nop
50: 10 68 00 2c b %xcc, 100 <main+0x100>
54: 01 00 00 00 nop
58: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
5c: 87 38 60 00 sra %g1, 0, %g3
60: 85 68 e0 05 sdivx %g3, 5, %g2
64: 82 10 00 02 mov %g2, %g1
68: 83 28 70 02 sllx %g1, 2, %g1
6c: 82 00 40 02 add %g1, %g2, %g1
70: 82 20 c0 01 sub %g3, %g1, %g1
74: 80 a0 60 00 cmp %g1, 0
78: 12 48 00 09 bne %icc, 9c <main+0x9c>
7c: 01 00 00 00 nop
80: 03 00 00 00 sethi %hi(0), %g1
80: R_SPARC_HI22 .rodata+0x10
84: 82 00 40 04 add %g1, %g4, %g1
88: 90 00 60 00 add %g1, 0, %o0
88: R_SPARC_LO10 .rodata+0x10
8c: 40 00 00 00 call 8c <main+0x8c>
8c: R_SPARC_WDISP30 puts
90: 01 00 00 00 nop
94: 10 68 00 1b b %xcc, 100 <main+0x100>
98: 01 00 00 00 nop
9c: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
a0: 87 38 60 00 sra %g1, 0, %g3
a4: 85 68 e0 03 sdivx %g3, 3, %g2
a8: 82 10 00 02 mov %g2, %g1
ac: 82 00 40 01 add %g1, %g1, %g1
b0: 82 00 40 02 add %g1, %g2, %g1
b4: 82 20 c0 01 sub %g3, %g1, %g1
b8: 80 a0 60 00 cmp %g1, 0
bc: 12 48 00 09 bne %icc, e0 <main+0xe0>
c0: 01 00 00 00 nop
c4: 03 00 00 00 sethi %hi(0), %g1
c4: R_SPARC_HI22 .rodata+0x18
c8: 82 00 40 04 add %g1, %g4, %g1
cc: 90 00 60 00 add %g1, 0, %o0
cc: R_SPARC_LO10 .rodata+0x18
d0: 40 00 00 00 call d0 <main+0xd0>
d0: R_SPARC_WDISP30 puts
d4: 01 00 00 00 nop
d8: 10 68 00 0a b %xcc, 100 <main+0x100>
dc: 01 00 00 00 nop
e0: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
e4: 85 38 60 00 sra %g1, 0, %g2
e8: 03 00 00 00 sethi %hi(0), %g1
e8: R_SPARC_HI22 .rodata+0x20
ec: 82 00 40 04 add %g1, %g4, %g1
f0: 90 00 60 00 add %g1, 0, %o0
f0: R_SPARC_LO10 .rodata+0x20
f4: 92 10 00 02 mov %g2, %o1
f8: 40 00 00 00 call f8 <main+0xf8>
f8: R_SPARC_WDISP30 printf
fc: 01 00 00 00 nop
100: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
104: 82 00 60 01 inc %g1
108: c2 27 a7 eb st %g1, [ %fp + 0x7eb ]
10c: c2 07 a7 eb ld [ %fp + 0x7eb ], %g1
110: 80 a0 60 64 cmp %g1, 0x64
114: 04 4f ff c0 ble %icc, 14 <main+0x14>
118: 01 00 00 00 nop
11c: 81 cf e0 08 rett %i7 + 8
120: 01 00 00 00 nop